logisim - 4-Bit ripple down counter using negative edge-triggered J-K flip flops - Electrical Engineering Stack Exchange
DeldSim - 4-Bit Up Counter
Design a 4-bit down counter (decrement by 1) and analyze for the same metrics. Assume that no enable signal is used in this case. Assume the same delay characteristic equation and hold
Synchronous counters
DeldSim - 4-Bit Down Counter
Digital Logic Design Engineering Electronics Engineering
How to design a 3-bit asynchronous counter using JK flip-flop - Quora
3 bit synchronous up/down counter using JK flipflop IC
Solved I need the Verilog code for 4 bit Synchronous Up/Down | Chegg.com